Design Of Hardware Efficient High Speed Multiplier Using Modified Ternary Logic
نویسندگان
چکیده
منابع مشابه
Design of High Speed Hardware Efficient 4-bit Sfq Multiplier
A 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. The circuit area of the multiplier designed with the Booth encoder method is compared to that ...
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ژورنال
عنوان ژورنال: Procedia Engineering
سال: 2012
ISSN: 1877-7058
DOI: 10.1016/j.proeng.2012.06.263